1. Field of the Invention
The present invention relates to simulation of a program of a processor and, more particularly, to a simulation method and simulation system of instruction scheduling.
2. Description of the Related Art
Upon developing an information processing system such as an SOC (System On Chip) including a high-speed processor, performance evaluation and operation inspection of the entire system including software must often be done before completion of the SOC as a target of development in some development processes. In order to attain accurate performance evaluation and operation inspection, simulation using a simulator, which is accurate in machine cycles and is called a CA (Cycle Accurate) simulator, is required. Upon execution of CAS (Cycle Accurate Simulation) using such CA simulator, i.e., upon execution of CA simulation, if a processor (e.g., a CPU) of the SOC as a target of performance evaluation and operation inspection is of a high-speed, high-performance one, an execution time about 5000 to 10,000 times of an actual operation time of this CPU after it is mounted is required.
In general, the CA simulator comprises an instruction emulator and instruction scheduler. The instruction emulator fetches and executes instructions of developed software, and the instructions executed by the instruction emulator are sent to the instruction scheduler. The instruction scheduler schedules the instructions sent from the instruction emulator. In this way, instructions, which are fetched and executed by the instruction emulator, are sent in turn to the instruction scheduler, which sequentially schedules instructions.
The CAS must accurately simulate, e.g., the behavior of a CPU (especially, an instruction scheduling process) in each machine cycle inside a simulator of the SOC. In order to implement accurate simulation, this scheduling process is necessary and indispensable. In the above arrangement of the CA simulator, the calculation time of the instruction emulator is around 1% of the total processing time in the CAS, but the calculation time of the instruction scheduler that sequentially executes scheduling accounts for most of the CAS.
For this reason, in the conventional technique, the execution time of instruction scheduling in the CAS becomes a bottleneck, and it is difficult to attain high-speed, accurate performance evaluation and operation inspection of the entire system.